2, October 2017

ESA Open Invitation to Tender AO8860
Open Date: 29/09/2017
Closing Date: 24/11/2017 13:00:00

Status: ISSUED
Reference Nr.: 16.1ED.05
Prog. Ref.: TRP
Budget Ref.: E/0901-01 – TRP
Tender Type: C
Price Range: 200-500 KEURO
Products: Satellites & Probes / On-board Data Management / On Board Data Management ¿ BB / General Purpose Programable Logic (PLD, FPGA)
Techology Domains: EEE Components and Quality / Methods and Processes for Product Assurance of EEE Components, including Radiation Hardness Assurance / Radiation Hardening
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Electrical Engineering Department
Division: Data Systems Division
Contract Officer: Fabrizi, Lavinia
Industrial Policy Measure: C2 – Activities in open competition, significant partecipat…
Last Update Date: 29/09/2017
Update Reason: Tender issue

Flash FPGAs combine the reprogrammability and flexibility of SRAM-based FPGAS, with immunity to configuration upsets, low static power and a non-volatile configuration, which are characteristics more common to antifuse-based FPGAs. The latest developments in Flash-based FPGAs, e.g. the 4th generation Microsemi Flash FPGAs (RTG4), offer a high number of high-performance programmable logic resources, large and fast on-board memories, and high performance I/O – SERDES, LVDS, DDR, etc. All the elements are very appealing in high-bandwidth data processing payload applications, but also high performance on-board computing, if these FPGA resources are combined with on-chip processors. Targeting 3rd generation (ProASIC3) and 4th generation (RTG4) Flash-based FPGA technologies, this activity includes the following tasks: 1.Development of (formal) verification methods for verifying the proper implementation of SEU/SETmitigation techniques applied at RTL level (e.g. TMR, ‘safe’ Finite State Machines, etc). Formal methods are indicated as a suitable solution for this problem as they present several advantages compared to stimulus-based simulation methods: the fact that they don’t require stimulus vectors in order to verify the equivalence of a mitigated design vs the original simplifies and shortens the verification task. Even more importantly, formal methods cover the complete design space exhaustively, hence their final proofs are more conclusive compared to simulation-based methods. 2.Preliminary radiation test campaign, targeting 4th generation Flash FPGAs, with the following aims:(a) Characterization of radiation-induced single event upsets (SEU) in I/O elements of the FPGA, and the effects ofpossible error mitigation techniques, such as TMR. © Characterization of radiation-induced errors on-chip RAM blocks: analysis of occurrence, and possible patterns, of single and multiple bit upsets in on-chip RAMs. (b) Characterization of PLL performance degradation (sensitivity) under radiation. It is preferred that The test vehicles used as Designs Under Test (DUTs) in this activity are beselected considering the intended use of these FPGAs in On-Board Computers (OBC) and data handling applications, and could include on-board interfaces such as SpaceWire/SpaceFibre and CAN, to other representative designs used in DH applications, that could facilitate the proposed tests.Procurement Policy: C(2) = A relevant participation (in terms of quality and quantity) of non-primes (incl. SMEs) is required. For additional information please go to EMITS news “Industrial Policy measures for non-primes, SMEs and RD entities in ESA programmes”.

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