ESA Open Invitation to Tender: 1-10557
Open Date: 05/10/2021 14:23 CEST
Closing Date: 17/11/2021 13:00 CEST

FPGAs/APSoC (All Programmable System on Chip) components are highly complex and very sensitive to single Event Effect (SEE), especially the configuration memory. Different techniques can be used to mitigate SEE in configuration memory such as internal scrubbing, readback and external scrubbing or blind reconfiguration. Nevertheless, the heavy ion or proton testing of these techniques is very difficult because of specific characteristics of the different particle accelerators (accelerated flux, pulsed beam, scanned beam…). It is, therefore, very challenging to analyse and understand the test results. In addition, very often assessment of SEE sensitivity is based on results available in literature, or based on tests with a specific test setup (i.e. vendor demonstration board) where the test conditions are often unknown or not directly comparable to the intended application.A flexible test setup will allow to mimic the SEE mitigation scheme intended in an application and synchronise the data acquisition with the irradiation. Then, an accurate assessment of the mitigation implemented is possible. This test setup will allow independent testing reproducing exactly SEE mitigation scheme intended on a given application and will be particularly useful for homogenizing radiation testing of state of the art COTS SoC, often used for Artificial Intelligence applications. The same setup will also allow performance of fault injection with realistic error signatures (as observed during irradiation tests) allowing for verification of mitigation strategies before the actual beam testing.This activity will then encompasses the following tasks:- Initial trade-off of possible FPGA based test setup solutions in order to optimize the flexibility and adaptability of the test setup,- An FPGA based test setup will be designed and built to test devices like Brave FPGA, Xilinx Kintex7 FPGAs and Zynq SoC,- Proton and heavy ion testing,- Fault injection testing,- Validation of the test setup through the assessment of the results of the testing tasks.

Directorate: Directorate of Tech, Eng. Quality
Estabilishment: ESTEC
ECOS Required: No
Classified: No
Price Range: 200-500 KEURO
Authorised Contact Person: Karine Magne-Lie
Initiating Service: TEC-QEC
IP Measure: N/A
Prog. Reference: E/0904-611 – GSTP Element 1 Dev
Tender Type: Open Competition
Open To Tenderers From: DE
Technology Keywords: 4-B-I-Effects Analysis Tools / 23-A-II-Radiation Hardening
Products Keywords: 2-F-1.1-a-General Purpose Microprocessors (ERC32, Leon 2) / 2-F-1.1-b-General Purpose Digital Signal Processors (e.g ADSP 21020, TMS320xx) / 2-F-1.1-c-Microcontrollers / 2-F-1.1-e-General Purpose Programable Logic (PLD, FPGA)