ESA Open Invitation to Tender AO9818
Open Date: 08/04/2019
Closing Date: 27/05/2019 13:00:00

Status: ISSUED
Reference Nr.: 19.1ED.04
Prog. Ref.: Technology Developme
Budget Ref.: E/0901-01 – Technology Developme
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+PL+EE+HU
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / Electronics / EEE Components / Discrete semiconductors (including diodes, transistors) / Satellites & Probes / Electronics / EEE Components / Monolithic Microcircuits (including MMICs)
Techology Domains: EEE Components and Quality / EEE Component Technologies / Wide Band Gap Technologies
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Electrical Department
Division: Data Syst & Microelectronics Division
Contract Officer: Erkelens-Sickinger, Franziska
Industrial Policy Measure: C1 – Activities in open competition limited to the non-Larg…
Last Update Date: 08/04/2019
Update Reason: Tender issue

High voltage and high switching speed DC-DC converters based on Gallium Nitride (GaN) technology offer a revolutionary breakthroughfor the next generation of power systems. Moving from Silicon (Si) to GaN, will mean power-conditioning subsystems with better efficiency and reduced mass/volume (50%). GaN transistors also offer the inherent ability to operate at higher voltages than Si and withimproved radiation tolerance. All of these attributes are important for space application. The application of this technology is useful for any missions requiring highly miniaturised power conversion subsystems with improved efficiency.At present, the externallyconnected gate driver topologies (e.g. Using bond wires, long PCB tracks) limit the useable switching frequency due to gate loop parasitics.A GaN die comprising of a half-bridge topology, i.e. Using 2 serial FET, meant to play respectively the role of switching andrectification in many space applicable power conversion topologies is needed. The die will also contain the gate driver circuit foreach FET. Such drivers are inherent to the interface between digital control signal and FET gate to source voltage. They must cope with source voltage floating with respect to control voltage.This activity encompasses the following tasks:Establish technical requirements of design, Process trials to allow monolithic integration. To include: Logic, Inverter, Protection circuitry, On chip passive components, Compatibility of interconnection metallisation between low power logic and high power switching functions.Building block functions shall be designed, simulated and characterised as separate entities Manufacture and test.Die used within a selectedpower switching converter to practically demonstrate the benefit of the monolithically integrated solution.Procurement Policy: C(1) = Activity restricted to non-prime contractors (incl. SMEs). For additional information please go to EMITS news “Industrial Policy measures for non-primes, SMEs and RD entities in ESA programmes”.