15, November 2019

ESA Open Invitation to Tender AO10122
Open Date: 12/11/2019
Closing Date: 16/01/2020 13:00:00

Status: ISSUED
Reference Nr.: 19.1ED.14
Prog. Ref.: GSTP Element 1 Dev
Budget Ref.: E/0904-611 – GSTP Element 1 Dev
Special Prov.: DE+FR
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / Electronics / EEE Components / Monolithic Microcircuits (including MMICs) / Satellites & Probes / Electronics / EEE Components / Hybrid circuits / Satellites & Probes / On-board Data Management / On Board Data Management ¿ BB / Microcontrollers
Technology Domains: Onboard Data Systems / Microelectronics for Digital and Analogue Applications / Digital and Analogue Devices and Technologies / EEE Components and Quality / EEE Component Technologies / Hybrids and Micropackaging
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Electrical Department
Division: Data Syst & Microelectronics Division
Contract Officer: Erkelens-Sickinger, Franziska
Industrial Policy Measure: N/A – Not apply
Last Update Date: 12/11/2019
Update Reason: Tender issue

The objective of the activity is to enable a validated European source for flip-chip wafer bumping for microelectronics packaging for VLSI technology (ASIC, FPGA, Memories, etc.) using a technology node of 28 nm or smaller. Semiconductor industry is moving to technologies (<65nm) where wire bonding will no longer be a suitable solution for components packaging. Flip-chip is seen as the only feasible solution for those technologies combining both low pitch and high I/Os number. Currently this technology with the adequate reliability level is only offered by subcontractors from the Far East which are mainly only accessible to non-European large semiconductor companies (Xilinx, Microsemi, etc..). The work to be performed is to identify, define and validate a European Flip chip technology able to provide wafer bumping services to both large and small semiconductor manufacturers. Flip-chip technology is widely available to commercial markets, the work to develop is to define and validate an existing flip-chip commercial technology up to space requirements. The proposed technology must cover both leaded solder bumps and Lead-free bumping. The target wafer dimensions would range from 8 to 12 inches diameter. Outcome of the activity shall be a space validated process identification document describing the technology ready to use in new component developments. The following tasks shall be done in the frame of this activity:- Technologyidentification and selection,- Samples manufacturing and Testing,- Release of a Process Identification Document for Space applications.NOTE: This activity is currently in the GSTP Work Plan but will only be implemented after confirmation of financial support from Delegations. The final list of participating states will be known at tender issue.

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