ESA Open Invitation to Tender AO9313
Open Date: 26/07/2018
Closing Date: 06/11/2018 13:00:00

Status: ISSUED
Reference Nr.: 18.1TT.46
Prog. Ref.: CC for Advanced Tech
Budget Ref.: E/0505-01C – CC for Advanced Tech
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+CA
Tender Type: C
Price Range: 200-500 KEURO
Products: Satellites & Probes / Electronics / EEE Components / Passive Microwave Devices (including for instance, mixers, couplers, isolators and switches)
Techology Domains: RF Systems, Payloads and Technologies / RF Technologies and Equipment / RF Equipment
Establishment: ESTEC
Directorate: Directorate Telecom & Integrated Applica
Department: Telecom Technologies,Product&Systems Dep
Division: Technologies and Products Division
Contract Officer: Dean, Andrea
Industrial Policy Measure: N/A – Not apply
Last Update Date: 26/07/2018
Update Reason: Tender issue

Objective:The objective of this activity is to design, manufacture and test a high spectral purity reference generator circuit enabling spurious free (or below the phase noise) operation of commercial of-the-shelf frequency synthesizers without phase noise degradation.Targeted Improvements:Enabling technology development of high spectral purity reference generators not existing today with spurious level below phase noise and no phase noise degradation.Description:The need for flexible local oscillators able to cope with the stringent frequency plan requirements of operators is becoming a must in modern flexible payloads and High Throughput Satellites. This requires the manufacturers of frequency converters to adopt more innovative frequency synthesizer solutions. Current preferred solutions are based on fractional-N synthesizers, however the frequency flexibility comes at the price of undesired spurious signals and degraded phase noise.This activity proposes a way to overcome this problem. A reference generator circuit (chip) shall be designed, manufactured and tested that is inserted between the reference oscillator and the reference input of the Phased Lock Loop (PLL). This circuit shall allow the PLL to achieve the equivalent of a fractional mode frequency selection (in small steps) with the phase noise and spurious performance of an integer mode operation PLL.A scaled engineering model of a high spectral purity reference generator shall be designed, manufactured and tested to validate the concepts developed.

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