ESA Open Invitation to Tender AO9440
Open Date: 11/07/2018
Closing Date: 24/09/2018 13:00:00

Status: ISSUED
Reference Nr.: 18.1ED.06
Prog. Ref.: Technology Developme
Budget Ref.: E/0901-01 – Technology Developme
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+PL+EE+HU
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / On-board Data Management / On Board Data Management / Payload Data Handling Units / Satellites & Probes / On-board Data Management / On Board Data Management ¿ BB / General Purpose Programable Logic (PLD, FPGA)
Techology Domains: Onboard Data Systems / Payload Data Processing / System Technologies for Payload Data Processing / Onboard Data Systems / Payload Data Processing / Hardware Technologies for Payload Data Processing / Onboard Data Systems / Payload Data Processing / Software Technologies for Payload Data Processing / Onboard Data Systems / Microelectronics for Digital and Analogue Applications / Digital and Analogue Devices and Technologies
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Electrical Engineering Department
Division: Data Systems Division
Contract Officer: Ferreol, Audrey
Industrial Policy Measure: C2 – Activities in open competition, significant partecipat…
Last Update Date: 11/07/2018
Update Reason: Tender issue

The SSDP ASIC, which is developed in the 2013-2016 (ASIC prototypes) and – 2017 (Flight Model ASICs) timeframe based on CTP funding, will include a LEON3 controller and 2 powerful fixed point Xentium(R) VLIW DSP cores providing a theoretical fixed-point processing power of >1.6 GOps. The DSP cores and peripheral interfaces are interconnected with a 3.2 Gbps on-chip network.In addition, to key features such as glue-less interfaces to next generation imager chips, the ASIC will also provide a fast bi-directional external peripheral interface (in the following called BEPI, ~800 Mbps) which is ideal for connecting the DSP to ADCs/DACs or FPGA based co-processors or digital frontends, as it is directly connected to the NoC interface and BEPI data traffic does therefore not interfere with memory accesses of the LEON3 controller or the DSPs. Input and output to/from BEPI are supported by NoC DMA which minimizes overheads. On the proposed board, the FPGA can be configured as a powerful co-processor (raw data provided via BEPI to FPGA, processed data returned via BEPI to SSDP) or a digital frontend (raw data fed via SpFi or other HSSL interface to FPGA, pre-processed data provided via BEPI to DSP). The LEON3 part of the DSP handles the platform interface (typically via redundant SpW) and provides overall data flow management, FDIR, and system management functions including FPGA re-configuration.Based on the requirements analysis for EO applications, application cases shall be selected for the prototyping phase and implemented in a combination of DSP software and FPGA firmware. These cases may include image processing / compression, multispectral data processing, and / or radar data processing.The board shall provide multiple standard interfaces (SpW, SpFi, other) and an architecture that keeps maximum flexibility for future EO applications prototyping. All selected components shall have space qualified equivalents to enable a fast development route towards EQMs and flight hardware.Apart from very high performance reliable data processing for optical and radar payloads in EO (up to many GOps/GFLOPs in specific applications), also applications in other areas (general reconfigurable data processing, optical navigation, ..) will benefit from the development.Procurement Policy: C(2) = A relevant participation (in terms of quality and quantity) of non-primes (incl. SMEs) is required. For additional information please go to EMITS news “Industrial Policy measures for non-primes, SMEs and RD entities in ESA programmes”.

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