ESA Open Invitation to Tender AO10190
Open Date: 20/07/2020
Closing Date: 20/10/2020 13:00:00

Status: ISSUED
Reference Nr.: 20.1TT.10
Prog. Ref.: CC-AT 4.0.1
Budget Ref.: E/0534-01G – CC-AT 4.0.1
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+CA+HU+PL
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / RF / Microwave Communication (Platform and Payloads) / “Communication – BB (Antennas excluded)” / Other
Technology Domains: RF Systems, Payloads and Technologies / RF Payloads / Telecommunication Payloads
Establishment: ECSAT
Directorate: Directorate Telecom & Integrated Applica
Department: Telecom Technologies,Product&Systems Dep
Division: Technologies and Products Division
Contract Officer: Beardsell, Andrea
Industrial Policy Measure: N/A – Not apply
Last Update Date: 20/07/2020
Update Reason: Tender issue

Objective: The objective of this activity is to develop and evaluate efficient digital beamforming algorithms and architectures forpayloads utilising digital processors. The developed concepts shall be implemented and tested on a representative digital processortestbed to demonstrate the power consumption improvement. Targeted Improvements: Reduction of power consumption by 50% with respect to current digital beamforming implementation. Reduction by 50% of the number of ASICs. Description: Current and future very highthroughput payloads need to simultaneously generate hundreds to thousands of beams over the coverage area, requiring a very large aggregated capacity (in the order of a few THz) to be beam-formed. Digital beamforming of such a large aggregated capacity is currently not possible due to the limited power available on-board and to thermal management challenges. Hence, current processors are onlyable to perform digital beamforming on a small portion of the total system capacity. Reduction of digital beamforming power consumptionwould allow the implementation of a full digital payload, resulting in many operational benefits and flexible capacity allocation, serving different users and applications. This activity will develop low-complexity, highly efficient algorithms, processing techniquesand architectures to significantly reduce power consumption, mass and volume and improve integration efficiency. Mathematical techniques combined with spatial symmetry of beams and spatial symmetry of radiating elements will be exploited to reduce the processing to a simple set of additions/subtractions, in many cases fully avoiding multiplication operations. A representative processor testbed will be developed and used to implement and test the developed algorithms and processing techniques.