ESA Open Invitation To Tender AO8750
Open Date: 26/10/2016
Closing Date: 21/12/2016 13:00:00

Status: ISSUED
Reference Nr.: 16.1ED.02
Prog. Ref.: TRP
Budget Ref.: E/0901-01 – TRP
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+PL+EE+HU
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / On-board Data Management / On Board Data Management / Central Data Management Units (CDMU) or Satellite Management Units (SMU)
Techology Domains: Onboard Data Systems / Onboard Data Management / Onboard Computers
Establishment: ESTEC
Directorate: Directorate of Technical & Quality Manag
Department: Electrical Engineering Department
Division: Data Systems Division
Contract Officer: Fabrizi, Lavinia
Industrial Policy Measure: N/A – Not apply
Last Update Date: 26/10/2016
Update Reason: Tender issue

The general approach while designing a Reconfigurable Avionics will follow the general principles:- Implementing by default most of the functions as SW- Using (slave) reprogrammable FPGA(s) as an accelerator to implement too CPU intensive functions- Providing a scalable and versatile I/O system supported by flexible SW drivers- Extending digital I/Os by Analogue Front-endsThe selected hardware platform is the combination of a powerful microprocessor and one or several high-end reconfigurable FPGAs, fulfilling the following needs:- Supporting exploratory and evolutionary designs according to mission needs during early development phases. The advantage at this stage is clearly to reduce costs thanks to using a flight representative and stable hardware platform based on SW defined functions off-loaded when required by blocks implemented in reprogrammable FPGAs- Allowing in-flight reconfigurations for the adaptation to different mission phases and modes. For instance, processing algorithms can be tuned according to evolving needs (science mission) or re-defined during the execution of the mission (e.g. for active de-orbiting).- Enabling a mission recuse in case of FDIR events or failures that could be rescued by a deep reconfiguration or the spacecraft core functions.The activity consists in developing at EBB level a HW module hosting a high end microprocessor, FPGAs and corresponding support equipment. A selection of IP Cores taken from ESA’s portfolio will be implemented and validated on the target.Eventually the Reconfigurable Data Handling core shall be part of the Compact Reconfigurable Avionics test bench installed in ESTEC’s Avionics Lab.

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