27, October 2016

ESA Open Invitation To Tender AO8799
Open Date: 25/10/2016
Closing Date: 20/12/2016 13:00:00


Status: ISSUED
Reference Nr.: 16.132.05
Prog. Ref.: TRP
Budget Ref.: E/0901-01 – TRP
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / On-board SW / Other
Techology Domains: Space System Software / Space Segment Software / Methods and Tools for Onboard Software Engineering Processes
Establishment: ESTEC
Directorate: Directorate of Technical & Quality Manag
Department: System, Software & Technology Department
Division: Software Systems Division
Contract Officer: Fabrizi, Lavinia
Industrial Policy Measure: N/A – Not apply
Last Update Date: 25/10/2016
Update Reason: Tender issue

The overall avionics activity, called Compact Reconfigurable Avionics (CoRA), comes from a technology push and shall demonstrate the flexibility, reliability and usefulness of a highly configurable system developed by using Model Based Avionics engineering technology targeting hardware based on a combination of the upcoming multicore processors and large space qualified reconfigurable FPGA(s).The use of the Compact Reconfigurable Avionics is to serve any mission, but the concept shall be demonstrated typically for small spacecrafts (typically 150 – 500 kg) to reduce the size of their avionics (data handling core and smart AOCS elements) while beingreliable (rad-hard).The Compact Reconfigurable Avionics is a set of 3 activities that, although issued as three different ITTs, shall be considered jointly, having the technical lead for each activity respectively in Software, Data Handling and AOCS.This Compact Reconfigurable Avionics Model Based Avionics Design activity covers the Software domain. It is aiming at developing a fully operational set of processes and tools supporting the definition and implementation of reconfigurable avionics. The processes and tools shall support the seamless integration of models developed in the frame of the Smart AOCS GNC Elements AOCS activity as wellas legacy source code (e.g. C and VHDL) and their deployment on the target hardware defined in the Reconfigurable Data Handling coreData Handling activity, i.e. a multicore processor connected to a reconfigurable FPGA.

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