CMOS IMAGE SENSOR BASED ON HIGH-RESISTIVITY EPITAXIAL SILICON
15, June 2018

ESA Open Invitation to Tender AO9442
Open Date: 14/06/2018
Closing Date: 31/08/2018 13:00:00

Status: ISSUED
Reference Nr.: 18.129.13
Prog. Ref.: GSTP Element 1 Dev
Budget Ref.: E/0904-611 – GSTP Element 1 Dev
Special Prov.: GB
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / AOCS & GNC / Sensors ¿ BB / Detectors (APS, CCD, infrared detectors, …) / Satellites & Probes / Payloads / Instruments / Optical Instruments / Imaging spectrometers
Techology Domains: Optoelectronics / Detector Technologies / Visible Detectors (mostly Si based)
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Mechanical Engineering Department
Division: Mechatronics and Optics Division
Contract Officer: Reinsoo, Anna
Industrial Policy Measure: N/A – Not apply
Last Update Date: 14/06/2018
Update Reason: Tender issue

The objective of the activity is the design, manufacture and characterisation of a CMOS image sensor based on high-resistivity epitaxial silicon.Visible image sensors with high sensitivity extending into the Near Infrared (NIR) are in high demand for many planned and future Earth observation and Science missions. The benefits of high-resistivity silicon in this area for CCDs has been previously demonstrated.The aim of this activity is to extend these benefits to CMOS image sensors and subsequently exploit the enhanced read-out capabilities and radiation tolerance which are inherent to CMOS image sensors.The benefits of the developed technology will be:1. Better electro-optical performance will be achieved, due to the use of thicker starting material e.g. increased Quantum Efficiency (QE) at higher energies (above ~3keV) or at long wavelengths (NIR).2. The possibility to achieve improved MTF performance by using appropriate processes and controlling the photodiode depletion with respect to the total thickness of the material.Emphasisshall be given to the schematic representation of the pixel layout as well as detailed detector architecture with schematics at transistor level of the main building blocks including pixel, column amplifier, programmable gain amplifier (if applicable), multiplexer and output amplifier. The pixel design with a schematic representation of metal layers and diffusion areas etc is expected to be based on detailed simulations and modelling of predicted performance.The following tasks will be done in the frame of this activity: – Detector specification and trade-off study. – Preliminary detector design and pixel simulation. – Detailed detector design. – Detector manufacture. – Detector characterization including radiation testing. – Evaluation, conclusions and recommendations.

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