ESA Open Invitation to Tender: 1-11018
Open Date: 17/05/2022 12:00 CEST
Closing Date: 28/06/2022 13:00 CEST

Estimate accurately the in-flight risk of stuck bits in SDRAM and DDR SDRAM, improve stuck bit testing and mitigation techniques and obtain stuck bit test data re-usable by all ESA missions.

Directorate: Directorate of Tech, Eng. Quality
Estabilishment: ESTEC
ECOS Required: No
Classified: No
Price Range: 200-500 KEURO
Authorised Contact Person: Karine Magne-Lie
Initiating Service: TEC-QEC
IP Measure: N/A
Prog. Reference: E/0901-01 – Technology Developme
Tender Type: Open Competition
Open To Tenderers From: AT+BE+CH+CZ+DE+DK+EE+GR+ES+FI+FR+GB+HU+IE+IT+LU+NL+NO+PL+PT+RO+SE
Technology Keywords: 23-A-V-RHA Process
Products Keywords: 2-B-1-h-Monolithic Microcircuits (including MMICs) / 2-F-1.1-g-High Density Memory Devices (e.g stacked SDRAM, FLASH)