ESA Open Invitation to Tender: 1-10722
Open Date: 07/06/2022 15:32 CEST
Closing Date: 05/09/2022 13:00 CEST

The objective of this activity is to evaluated a new class of component: „ACAP” (Adaptive Compute Acceleration Platform) for on-board RF processing and machine learning applications. A breadboard shall be developed and tested with representative on-board interfaces and fault-tolerance techniques. Targeted Improvements: A factor of 5 to 7 increase of digital signal processing performance and 50% improvement of power consumption efficiency versus the current state-of-the-art COTS FPGAs for RF applications. Description: Today field programmable gate arrays (FPGA) offer the flexibility to realise many on-board functions, including software defined radios. However, the current generation of FPGAs available for space are not suitable for an efficient realisation of applications such as:- high throughput 5G nodes on satellites;- machine-to-machine/Internet-of-things applications on small platforms having limited resources;- wideband RF signal identification using machine learning. Adaptive Compute Acceleration Platform (ACAP) devices could enable the above applications. They combine digital-signal-processor-enabled FPGAs with high-speed digital interfaces and hardware machine learning accelerators, integrated into a single device. Existing devices have been developed for terrestrial 5G wireless applications and for other applications, such as data centres, wired networks and automotive driver assist applications. The available devices include multiple 37.5 Gbit/s transceivers, with a total of tens of Tbit/s in serial data throughput, as well as integrated blocks for forward error correction for high-throughput implementations of low density parity check codes, polar, turbo codes, etc.This activity will evaluate this new class of components for on-board RF processing and machine learning applications. In a first step, the activity will select and evaluate a component of the ACAP family. Radiation testing and characterisation will be performed, including single event latch-up, single event upset and total ionizing dose. In a second step, an elegant breadboard will be developed with representative data, control interfaces and fault-tolerance functions. At least one application will be selected and a test-bed will be developed to evaluate and benchmark the performance using emulated real-time RF data. The radiation test results will be available for the Agency to distribute upon request to companies in ESA member states.

Directorate: Directorate Telecom Integrated Applica
Estabilishment: ESTEC
ECOS Required: No
Classified: No
Price Range: > 500 KEURO
Authorised Contact Person: Florence Odette Jeanne Glandieres
Initiating Service: TIA-TTS
IP Measure: N/A
Prog. Reference: E/0534-01G – CC-AT 4.0.1
Tender Type: Open Competition
Open To Tenderers From: AT+BE+CA+CH+CZ+DE+DK+GR+ES+FI+FR+GB+HU+IE+IT+LU+NL+NO+PL+PT+RO+SE
Technology Keywords: 1-A-II-Hardware Technologies for Payload Data Processing
Products Keywords: 2-F-1.1-e-General Purpose Programable Logic (PLD, FPGA)