ESA Open Invitation to Tender AO10569
Open Date: 14/01/2021
Closing Date: 25/02/2021 13:00:00

Status: ISSUED
Reference Nr.: 20.1ED.11
Prog. Ref.: GSTP Element 1 Dev
Budget Ref.: E/0904-611 – GSTP Element 1 Dev
Special Prov.: DE
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / Electronics / EEE Components / Other
Technology Domains: Onboard Data Systems / Microelectronics for Digital and Analogue Applications / Methodologies
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Electrical Department
Division: Data Syst & Microelectronics Division
Contract Officer: Seynaeve, Christophe Rene R.
Industrial Policy Measure: N/A – Not apply
Last Update Date: 14/01/2021
Update Reason: Tender issue

New FPGA devices suitable for on-board use offer the possibility of being many times reconfigurable, in particular flash or SRAM: Microsemi RTG4; Xilinx KU60; NanoXplore BRAVE FPGA, are selected for their high performance data processing capabilities. This allowsto change its functionality, to save resources by dynamically reprograming and running different applications or introduce algorithmic improvements after the instruments are flying.FPGA on-board reconfiguration involves uploading a new bitstream and programming it onto the FPGA, following strategies that differ depending on the FPGA technology. Although guidelines and tools are provided by the vendors, the challenges of re-configuring on-board, in radiation environment with extreme temperatures is not always addressed. SEE and TID can affect the reconfiguration and might lead to unsuccessful configuration or even total destruction of the FPGA or othercomponents on the same board.The following main tasks are proposed for each of the target technologies (flash RTG4; SRAM Xilinx andNanoXplore):-Identification of reconfiguration methods for the target technologies, and their characterization in terms of reconfiguration times, feasibility of partial reconfiguration, available protocols.-Assessment of the probability of SEE (destructive andnon-destructive) during re-configuration in radiation environment as well as aging effects due to TID; taking into account information provided by vendors and conducting independent radiation and temperature tests.-Propose a strategy for safe FPGA onboard reconfiguration, addressing system level aspects of total or partial FPGA reconfiguration (considering also systems with one or multipleFPGAs or using FPGAs as co-processor accelerators), including: – time and bandwidth required to upload a full or partial bitstream, and compression schemes for missions with low upload data rates; – safe storage of bitstream in memory; – prevention and detectionof corruption in the programmed file (built in self tests); – fault isolation schemes at unit level that prevent possible damages caused by a faulty bitstream being configured; – operational aspects related to the FPGA being unavailable during reconfiguration.-The design of a boot loader that implements TM/TC functionality to execute the necessary steps from the upload of the bitstream tobecoming operational with a new configuration, as detailed above. Investigation of the optimal computing platform within the spacecraft which should execute such boot loader.