ESA Open Invitation to Tender AO10449
Open Date: 30/07/2020
Closing Date: 08/10/2020 13:00:00

Status: ISSUED
Reference Nr.: 20.1ED.09
Prog. Ref.: Technology Developme
Budget Ref.: E/0901-01 – Technology Developme
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+PL+EE+HU
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / On-board Data Management / On Board Data Management ¿ BB / Onboard Communcation (MIL-STD-1553, CAN, SpW, Sensor Bus, Wireless)
Technology Domains: Onboard Data Systems / Onboard Data Management / Onboard Networks and Control/Monitoring / Onboard Data Systems / Microelectronics for Digital and Analogue Applications / Digital and Analogue Devices and Technologies
Establishment: ESTEC
Directorate: Directorate of Tech, Eng. & Quality
Department: Electrical Department
Division: Data Syst & Microelectronics Division
Contract Officer: Singer, Anze
Industrial Policy Measure: N/A – Not apply
Last Update Date: 30/07/2020
Update Reason: Tender issue

On-board communication via serial link protocols such as SpaceFibre require Serializer/Deserializer (SERDES) at the physical layer,which connects two units (e.g. payload instrument, mass memory) via copper, backplanes, or optical transceivers with each other.Currently, the maximum length of the medium is severely limited for high speed links in the excess of 2 Gbps due to transmission line losses. In addition, costly complex FPGAs and ASICs with high speed serial capability are more exposed to damage in case of fault conditions experienced at one of the end-points. Thus, there is a need to develop a new device providing the repeater function to compensate losses and to prevent fault propagation, and the multiplexer/switch functions to enable robust redundancy configuration. Thisnew IC shall operate with all SERDES compliant to the standard ECSS-E-ST-50-11C SpaceFibre standard (data rates of up to at least6.25 Gbps) but can also be used for other protocols such as SRIO, PCIe and Ethernet. This activity encompasses the following tasks: – requirements consolidation based on user needs. – trade-off between available radiation-hardened chip technologies. – IC design and packaging. – performance characterisation to ensure compliance with ECSS-E-ST-50-11C. – development plan.