ESA Open Invitation To Tender AO8718
Open Date: 13/07/2016
Closing Date: 26/09/2016 13:00:00

Status: ISSUED
Reference Nr.: 16.1QM.14
Prog. Ref.: TRP
Budget Ref.: E/0901-01 – TRP
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+PL+EE+HU
Tender Type: C
Price Range: 200-500 KEURO
Products: Satellites & Probes / Electronics / EEE Components / Monolithic Microcircuits (including MMICs)
Technology Domains: EEE Components and Quality / EEE Component Technologies / Wide Band Gap Technologies
Establishment: ESTEC
Directorate: Directorate of Technical & Quality Management
Department: Product Assurance and Safety Department
Division: Materials & Components Technology Division
Contract Officer: Strzelecki, Patryk Michal
Industrial Policy Measure: C1 – Activities in open competition limited to the non-Larg…
Last Update Date: 13/07/2016
Update Reason: Tender issue

In most RF or DC power converter device scenarios, heat is not generated uniformly or distributed equally across the semiconductor die. Instead a very large thermal gradient exists, with the largest thermal flux density being close to the transistor semiconductor channel or junction. The performance (power density, reliability etc) of electronic devices is fundamentally limited by this close to junction thermal transport process, often leading to unacceptably high operating temperatures unless device operation is significantly derated. This close to junction thermal gradient will become even more of a problem as high power wide band gap semiconductors begin to be introduced into future space systems. The conventional solution for thermal management is to attach these semiconductords to off chip heat spreaders, that require heat to be extracted through and across the entire area of the transistor chip. Even with the use of high thermal conductivity semiconductor substrates, such as SiC, 60 to 70% of the temperature drop occurs between the transistor junction and the back-face of the semiconductor die, typically within a distance of only1 to 2μm from the transistor channel. The objective of this activity is to explore disruptive thermal management techniques and technologies that can be applied as part of the semiconductor manufacturing process. These approaches will be aimed at mitigating thermal bottlenecks, close to the heat generating source (i.e. within a few μm’s from the transistor channel). Since the transistors will be able to operate at a lower temperature, this will allow higher gain, higher efficiency, reduced on-state resistance and higher output power for a given transistor size; significantly reducing size, mass and power consumption at system level. These thermal limitations will be alleviated by introducing thermal management techniques within the semiconductor interlayers, by optimizing the substrate to semiconductor interface and by investigating novel transistor layout approaches for improved thermal heat spreading Successful completion of this program will close the gap between chip-level heat generation density and system-level heat removal density in high-performance electronic systems, power electronics, RF electronics, MMIC, power amplifiers and solid-state lasers. o overcome such problems, a program of work to investigate the following areas shall be initiated:- Demonstration of improvements in device performance by undertaking fabrication trials to evaluate and demonstrate novel thermal management techniques at the semiconductor device level. To include:- Optimisation of epitaxy nucleation layer (between SiC and GaN) since this currently is a major thermal barrier. It has been reported that up to 30% of the total temperature gradient can occur across non-optimised nucleation layers [Kuball et al. 2010]- Growth and/or insertion of heat sink layers, e.g. CVD diamond films, as close to the active channel/device junction area as possible or deposited on top of the semiconductor die.- Implementation of thermal vias, thermal bus-bars for lateral heat spreading- Growth of power transistors on improved thermal conductivity substrates, e.g. diamond, or the use of wafer bonding techniques to attach e.g. GaAs or GaN HEMT epitaxial layers to very high thermal conductivity substrates.- Use of Micro-fluidic techniques or micro-channels etched below the active device area containing fluid for use in a forced cooling loop- Feasibility assessment for introduction of thermoelectric cooling cells within the region of the semiconductor junction- Device processing/fabrication trials- Undertaking appropriate measurements to assess device performance. Procurement Policy: C(1) = Activity restricted to non-prime contractors (incl. SMEs). For additional information please go to EMITS news „Industrial Policy measures for non-primes, SMEs and RD entities in ESA programmes”.

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